1. Field
This disclosure relates generally to semiconductors, and more specifically, to the control of a data strobe signal used by synchronous storage circuitry.
2. Related Art
Synchronous dynamic random access memory (SDRAM) operate synchronously with a system clock in a data processing system. The input and output of the SDRAM are synchronized to an active edge of a system clock. Double data rate (DDR) SDRAMs allow data transfers on both a rising and a falling edge of a clock and thus provide twice as much data as an SDRAM.
Conventional DDR SDRAMs use a bidirectional data strobe signal commonly referred to as a DQS signal. A data strobe receiver receives the DQS signal from either SDRAM or a memory controller and functions to provide the DQS signal so that valid data is centered about DQS transitions meeting setup and hold time requirements of the SDRAM.
For example, DDR SDRAM memory controllers and SDRAM use the DQS strobe signals to send data to the SDRAM (write transfers) and receive data from the SDRAM (read transfers). The DQS data strobe signal functions to capture data as being input or output on each edge of the DQS data strobe signal. It is a requirement of industry standards that data be centered about DQS transitions meeting setup and hold time requirements of the SDRAM for write transfers performed by an SDRAM controller. Industry standards define several states of DQS before, during and after a burst transfer of data. Before a burst transfer of data, DQS is in a high-impedance state that is known as Hi-Z. When DQS is in Hi-Z, DQS is not driven by the memory controller or SDRAM and therefore has an indeterminate voltage level. In a clock cycle before a burst data transfer, DQS transitions from the Hi-Z high-impedance state to a logic low. This logic low state is known as a data strobe preamble. After the data strobe preamble, DQS transitions are used to synchronize the transferred data. At a half clock before the data transfer is complete, DQS remains in a logic low state. This state is known as a data strobe postamble. After completion of the postamble, the DQS data strobe signal again enters the Hi-Z high-impedance state. Because the DQS strobe signal is not driven until the data strobe preamble starts and is stopped at the end of a transaction in the postamble, it is important that a data strobe receiver be turned on and off at the correct time in order to generate a DQS strobe signal with the correct timing. Otherwise indeterminate control signal values may be generated or the DQS strobe signal may oscillate and thereby result in erroneous latching of information.
A well known JEDEC specification for dynamic random access memories (DRAM) is the DDR3 specification, JESD79-3. This specification describes a write leveling sequence that allows the DDR controller to calibrate the launch time of the DQS strobe signal and associated data bits such that they will arrive from the memory controller to the DRAM within a required timing window. This timing window is further described in the JEDEC tDQSS specification to be within plus or minus twenty-five percent of the rising edge of a memory clock. This calibration sequence is especially useful for DDR3 which uses fly-by routing on DDR3 dual in-line memory modules (DIMMS). However, before starting the write leveling sequence, the controller must have the ability to launch (i.e. a start point in time) each DQS strobe signal such that it arrives within a predefined timing window at the DRAM. At slower DDR3 frequencies, it may be possible to have one start point for all DQS strobe signals. However, for higher DDR3 frequencies, each strobe may require a separate start point. To accomplish the start point, each strobe is required to be separately programmed which requires information regarding the physical properties of a memory system and its individual components. Additionally, programming time and effort is required as well as storage for each starting point.